Modeling and Simulation Simulink for Model-Based Design enables you to reduce development time for AMD FPGA and Zynq SoC applications by modeling the hardware implementation at a high-level …

Oct 15, 2025 · HDL coder also provides integration with Xilinx tools to integrate the generated HDL IP core into the FPGA or SoC reference designs to generate bitstream that you can directly download …

This example shows how to generate and run code from a Simulink® model onto an AMD Zynq® ZC702 evaluation kit with a VxWorks® 7 operating system.

Supported Hardware Platforms AMD Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit + XM500 Balun card. Design Task In this example, the design task is to implement a GPS acquisition system on an …

SoC Blockset Support Package for AMD FPGA and SoC Devices enables you to design, evaluate, and implement SoC hardware and software architectures on AMD FPGAs and AMD Zynq ® SoCs and …

2 days ago · This example shows how to use the hardware-software co-design workflow to blink LEDs at various frequencies on the Xilinx® Zynq® ZC702 evaluation kit.

This example shows how to build a custom Linux® image for an HDL Coder IP core by using the MathWorks® build system for the Digilent Zybo Z7-10 Zynq® board.

Introduction SoC Blockset supports a subset of SoC and FPGA boards. To support custom boards, such as a board with different DDR memory or IO devices, SoC Blockset provides generalized APIs. This …

Create RFSoC HDL Coder Models This workflow customizes and designs an RFSoC model using the Zynq RFSoC Template Builder tool. This figure shows all of the interfaces that you can model by …

This example shows how to implement wireless communication algorithms on the Zynq® radio platform that are partitioned across the ARM® processing system and the FPGA programmable logic. A …